1. Field of the Invention
The invention relates generally to low-noise amplifiers and more specifically to low-noise amplifiers having predistortion circuitry.
2. Prior Art
Highly linear circuits are of paramount importance in RF systems, as nonlinearity causes many problems, including, among others, harmonic generation, gain compression, desensitization, blocking, cross modulation and intermodulation. Several linearization techniques have been introduced, especially in Power Amplifier (PA) design. However, despite their explicit improvement in linearity, their complex structure (usually based on sophisticated feedback schemes), does not allow them to be used in LNA designs where low noise requirements are of prime importance.
An elegant LNA linearization technique is the derivative superposition method. The CMOS implementation of the technique is effective at relatively low frequencies due to the large transistors required, whereas in a BiCMOS technology, the technique might be used at higher frequencies. An alternative method of predistortion using the technique of adaptive gate biasing is proposed for a 900 MHz LNA design. Unfortunately, the method is limited to operation frequencies below 2 GHz due to speed problems at higher frequencies. A shunt FET predistortion branch can be used for PA linearization. In such a design, the 3rd-order derivative of the predistortion branch transfer function is used to partially cancel the third-order intermodulation distortion (IMD3) response generated by the main amplifier. A significant improvement in the third order input intercept point (IIP3) value is observed, at the expense of reduced gain in the passband. In addition, phase delay problems at high frequencies negate the linearization effect, limiting the applicability of the topology.
A single, shunt transistor predistorter (STP) 120 is shown with respect to a prior art linearized low noise amplifier 100, shown in FIG. 1. The main amplifier is a 1-V LNA 110 design. The drain current id can be characterized by a Taylor series expansion of the gate voltage around the bias point. The output current is approximated by:
                                          i            d                    ⁡                      (                          v              g                        )                          =                                                            ⅆ                                  I                  d                                                            ⅆ                                  V                  g                                                      ⁢                          ❘                                                V                  g                                =                                  V                  G                                                      ⁢                                                            v                  g                                +                                                      1                    2                                    ⁢                                                                                    ⅆ                        2                                            ⁢                                              I                        d                                                                                    ⅆ                                              V                        g                        2                                                                                                        ⁢                              ❘                                                      V                    g                                    =                                      V                    G                                                              ⁢                                                                    v                    g                    2                                    +                                                            1                      6                                        ⁢                                                                                            ⅆ                          3                                                ⁢                                                  I                          d                                                                                            ⅆ                                                  V                          g                          3                                                                                                                    ⁢                                  ❘                                                            V                      g                                        =                                          V                      G                                                                      ⁢                                  v                  g                  3                                                              =                                                    g                m                                  (                  1                  )                                            ⁢                              v                g                                      +                                          g                m                                  (                  2                  )                                            ⁢                              v                g                2                                      +                                          g                m                                  (                  3                  )                                            ⁢                              v                g                3                                                                        (        1        )            Id and Vg are the large signal drain current and gate voltage, vg and id are incremental gate-voltage and drain-current respectively around the quiescent bias point (ID, VG) and gm(n) indicates the nth order derivative of Id with respect to Vg. Under appropriate biasing, M2 is used to generate the opposite polarity IMD3 signal with respect to that of M1, and is utilized for LNA linearization by IMD3 product cancellation.
The topology achieves a large increase in linearity performance with a significant decrease in power gain (˜1.78 dB). The topology suffers severely from phase delay problems at high frequencies, and this negates the linearization effect. Finally, the linearization depends on the gm(3) value, which is degraded severely around the optimum bias point, leading to linearity degradation. It would therefore be advantageous to provide predistortion circuitry that would overcome the shortcomings of the prior art.